Microelectronics Momentum Drives the Nation’s Semiconductor Resurgence
Georgia Tech drives trailblazing chip research and nurtures the future microelectronics workforce that are key to America’s long-term semiconductor competitiveness
The world’s dependence on semiconductors came into sharp focus in 2021, when automotive manufacturing ground to a halt because of massive computer chip shortages – as Asian suppliers couldn’t keep up with demand for microelectronics – miniaturized electronic circuits and components that drive everything from smartphones to new vehicle components to hypersonics weapons systems.
The culprit was global supply chain disruptions caused by the Covid-19 pandemic. The crisis has highlighted the pressing need for the U.S. to bolster its domestic semiconductor supply chains and industrial capacity, after three decades of decline as a semiconductor producer. The U.S. share of global semiconductor fabrication has dropped to 12% today, compared to 37% in 1990, according to the Semiconductor Industry Association (SIA). In addition, the semiconductor industry today only accounts for 250,000 direct U.S. jobs.
As the country rebuilds its semiconductor infrastructure at home, Georgia Tech serves as a vital partner – to train the microelectronics workforce, drive future microelectronics advances, and provide unique fabrication and packaging facilities for industry, academic and government partners to develop and test new solutions.
Georgia Tech is driving future microelectronics advances while providing unique fabrication and packaging facilities to industry partners. Here, Madhavan Swaminathan, director of the 3D Systems Packaging Research Center, outside the Pettit Microelectronics Building Cleanroom facility. (Photo credit: Allison Carter, Georgia Tech)
“We’re one of the only universities that can support the whole microelectronics stack – from new materials and devices to packaging and systems,” said Madhavan Swaminathan, the John Pippin Chair in Microsystems Packaging in the School of Electrical and Computer Engineering and director of the 3D Systems Packaging Research Center.
Swaminathan, an IEEE Fellow and former IBM expert on packaging for supercomputers, observed that in today’s complex semiconductor sector, it’s not enough to focus on a single device or process since they must coexist in a stack with other devices and processes as part of a larger system.
“When you have a stack, innovations can come from a top-down or bottom-up direction, and both are critical,” said Swaminathan. “At the top of the stack are applications that drive the technologies. But sometimes it can start at the bottom and go up such as when you develop a new material, device, or packaging technology that can improve existing applications.”
Engineering and Science Research Strengths
Georgia Tech is well positioned to support collaborative efforts by industry and government to strengthen the country’s semiconductor capacity as Congress considers ways to fund the previously passed Creating Helpful Incentives to Produce Semiconductors for America and Foundries Act (or the CHIPS for America Act), which will fund semiconductor research, design, and manufacturing initiatives.
(L to R) Oliver Brand, executive director of Georgia Tech’s Institute for Electronics and Nanotechnology, Madhavan Swaminathan, John Pippin Chair in Electromagnetics in the School of Electrical and Computer Engineering, and Shimeng Yu, ECE associate professor, in the Pettit Microelectronics Building Measurement and Characterization Lab. The Keyence Profilometer is shown in the foreground. (Photo credit: Robert Felt, Georgia Tech)
Oliver Brand, electrical engineering professor and executive director of Georgia Tech’s Institute for Electronics and Nanotechnology, notes that Georgia Tech’s large engineering and science faculty bring a broad set of research expertise to this significant industry challenge. Supporting such a diverse research agenda requires robust facilities, which Georgia Tech is uniquely positioned to provide.
“We have one of the largest academic cleanroom facilities in the country and the largest in the Southeast,” said Brand. Importantly, these cleanrooms and an associated materials characterization facility are open to users from industry, academia and government labs. “Georgia Tech serves as a site and coordinating office of the NSF-funded National Nanotechnology Coordinated Infrastructure (NNCI) program, a national network of nanofabrication and characterization facilities,” Brand emphasized.
Georgia Tech employs a strong support staff, from the technician level to the engineer and research faculty level. “We have incredible staff expertise that supports the tools, users and research activities,” Brand said.
From Lab to Fab: Georgia Tech’s Facilities Support Faster Commercialization
Georgia Tech prides itself on providing laboratory to fabrication capabilities enabled in part by one of the Institute’s crown jewels – the 3D Systems Packaging Research Center, which has grown into a globally recognized research center for advanced packaging and system integration.
“The Center cuts across seven schools and is a highly interdisciplinary research center,” noted Swaminathan, who pointed out that one in every three students working at the Center are undergraduate students. Some 50 graduate and undergraduate students and several visiting engineers rely on the Center, which is operated by 11 research/administrative staff.
The Center works with 41 companies around the world today, as well 14 universities and several federal agencies.
“The Center has a very collaborative set of partners from industry. They investigate problems from a manufacturing angle, a technical angle, and a demonstration angle. That’s a unique way of looking at how to drive innovation forward,” said Ravi Mahajan, currently an Intel Fellow for High-Density Interconnect Pathfinding who also was a founding PRC industry consortia member 27 years ago.
Mahajan applauded Georgia Tech faculty for their expertise and collaborative spirit, as well as their ability to train the future semiconductor engineering workforce.
“The students we've hired from Georgia Tech have hit the ground running. They are trained to work in industry, and I give a lot of credit to Georgia Tech faculty for training them that way. In fact, one of Georgia Tech's alumni is now an Intel Fellow, one of the highest levels of technical achievement at Intel. It speaks volumes to the quality of engineering talent that comes to us from Georgia Tech,” he said.
Read more about how Georgia Tech researchers are leading the next wave of semiconductor innovation and chip security.
Semiconductor Market Impact
Georgia Tech’s packaging smarts are driving measurable investments in Georgia and around the country. For instance, the Center’s pioneering work in glass as a semiconductor packaging solution has resulted in a $473 million semiconductor investment led by Korean company SKC, which will open a glass substrate manufacturing facility in Covington, Georgia, that will employ 400 people. The Center laid the groundwork for this venture by proving that glass-based substrates could be less costly and support higher performance as compared to silicon or other packaging materials.
On the defense side, Qorvo, a leader in miniaturized radio frequency (RF) components for commercial and defense users, leveraged the Packaging Research Center to win the SHIP (State-of-the-Art Heterogeneous Integrated Packaging) contract awarded by the Naval Surface Warfare Center (NSWC). Under the program, Qorvo will develop a production and prototyping center for RF assemblies in Richardson, a city in Dallas, Texas. The program, valued at up to $75 million, is designed to enhance the United States’ edge in technology and national security.
"In our SHIP proposal, we were evaluating what the next-generation of RF-optimized packaging and in particular, substrate technology, would look like,” recalled Andrew Ketterson, research fellow in Qorvo’s Infrastructure and Defense Products Research group.
Qorvo proposed glass core technology with advanced build-up layers that the PRC has been developing over many years. According to Ketterson, the PRC helped introduce the technology to Qorvo and assisted in the company’s winning SHIP proposal and later, advising the firm during the trade study phase that included refining Qorvo’s original advanced technology (AT) approach and plan.
“This effort led to additional funding under SHIP to expand the scope and depth of our original proposal,” said Ketterson.
He noted that Qorvo could have funded one professor at a university, but through the PRC, his team gains access to the whole team as well as access to process and materials knowhow, tools and facilities for substrate prototyping, material and tool vendors and the latest packaging research over a wider area beyond RF.
IEN technical staff in the Nanofabrication Cleanroom in the Marcus Nanotechnology Building. (Photo credit: Christa Ernst, Georgia Tech)
Better Equipment Leads to Faster Chip Fabrication
Over the past three years, Georgia Tech has invested $3 million to upgrade and modernize its lithography capabilities. The new equipment automatically patterns a thin layer of polymer that is either sensitive to light or sensitive to an electron beam.
The new lithography systems allow researchers to instantly send a file to the machine, which directly writes the pattern and prints it compared with the previous manual process involving photomasks that took a week.
“The turnaround time for the researchers is much, much quicker. In fact, they’ve said it has redefined how they do research because they can iterate designs much more quickly,” Brand said.
Looking ahead, Brand and Swaminathan envision Georgia Tech becoming an epicenter of U.S. innovation in semiconductors and packaging as the country begins to reclaim a leadership position as a semiconductor manufacturer.
“Georgia Tech is well positioned to be a key partner and workforce developer as we tackle fundamental, applied and translational research on the latest advances related to devices and packaging in microelectronics,” said Swaminathan. “Our infrastructure – both in skilled personnel and in a shared facility model that facilitates fast technology transfer from prototypes to manufacturing – will be key as the United States looks to accelerate its microelectronics capacity.”
Media Relations Contact and Writer: Anne Wainscott-Sargent (404-435-5784) (firstname.lastname@example.org)