Bayesian Learning Applied to Semiconductor Packaging

Electronics have permeated nearly every part of our lives from medicine to entertainment to the way we work. As the uses of electronics increase, so does the need for highly specialized electronic components. Now, a new method for optimizing electronics has been developed that will dramatically cut the time that it takes to get new components and systems to market. 

Traditionally, electric components and systems, such as semiconductors and chips, are tuned and tested over months before they are optimized for a task. A new method developed by Madhavan Swaminathan and his students — which is now available to companies as a software program — uses a statistical technique based on probabilities called Bayesian optimization to replace the usual trial-and-error method.

Swaminathan is the John Pippin Chair in Electromagnetics and Microsystems Packaging in the Georgia Tech School of Electrical and Computer Engineering (ECE) and the Director of the 3D Systems Packaging Research Center. He developed this software in collaboration with his graduate students and his collaborators in the Center for Advanced Electronics through Machine Learning (CAEML), which is part of the National Science Foundation (NSF)-funded Industry-University Cooperative Research Centers (IUCRC) program; Swaminathan serves as the Site Director for CAEML. The NSF IUCRC program enables cutting-edge research on emerging technologies to benefit manufacturing sectors.

Read more about Swaminathan’s project on the NSF IUCRC website