Researchers at the Georgia Institute of Technology are developing a wideband four-channel millimeter wave transmit-receive (T/R) module based on silicon-germanium (SiGe) technology that will support active electronically-scanned arrays (AESA) for potential military applications.

Designed to operate between 18 GHz and 50 GHz, the module could help address threat systems operating at millimeter wave frequencies and provide to military applications many of the advantages that millimeter wave technology is bringing to commercial applications such as 5G wireless, internet-of-things devices, and radar-based vehicle collision avoidance systems.

“The goal is to demonstrate small size, weight, power, and cost in a wideband millimeter wave T/R module,” said Paul Jo, a Georgia Tech Research Institute (GTRI) research engineer who is leading the project. “This would be a major module at the front of the AESA system, right behind the radiator element to process signals.”

Known as Millimeter Wave Active Electronically Scanned Array using Silicon-Germanium Transmit/Receive Modules (MAESTRO), the project represents a collaboration of GTRI and SiGe specialists in Georgia Tech’s School of Electrical and Computer Engineering. The use of SiGe helps support the high level of integration necessary for the miniaturization required by the module’s high-frequency operation.

“When it comes to millimeter wave frequencies, the AESA element lattice is less than one centimeter in size, and at 50 GHz, it’s three millimeters, which is very challenging to work with,” Jo noted. “That forces an extreme level of integration and miniaturization for this T/R system, which we are addressing through design and fabrication of the small SiGe monolithic microwave integrated circuit (MMIC) die.”

The researchers recently completed the fabrication and packaging of a core channel T/R module die, and are designing an evaluation board to demonstrate performance of the module. Also completed is the fabrication of a stand-alone radiator board for wideband and high-frequency applications; that evaluation board also is under test.

Wideband AESAs are an enabling technology for current and future military radar and communications systems by providing rapid beam steering, graceful degradation, electronic production, and low probability of intercept. The atmospheric attenuation of radio-frequency (RF) signals at millimeter wave frequencies is much greater than at microwave frequencies. As a result, high-gain directional apertures such as AESAs are required to propagate energy over tactically relevant distances.

Beyond the high level of integration, the system presents technical challenges related to manufacturing, packaging, and thermal management. For packaging MAESTRO, the research team is evaluating a Flip-Chip Ball Grid Array (FCBGA) solution to reduce the signal path from the die to the printed circuit board.

Earlier in the four-year project, the research team designed and fabricated single-channel and four-channel T/R modules and measured the RF performance of a chip-on-board (CoB)-assembled single-channel T/R module. The measured results confirmed that the designed digital control circuitry works for both Tx and Rx modes – attenuation and true-time delay – and that the time delay was consistent across the target bandwidth.

The MAESTRO program is a collaboration between GTRI and the research team of John Cressler, a Regents Professor at the Georgia Tech School of Electrical and Computer Engineering. Cressler’s team specializes in SiGe for heterojunction bipolar devices designed to provide high-frequency performance in mixed-signal circuit and analog circuit ICs.

“Silicon is a standard technology that industry is using to integrate very complicated systems,” Jo noted. “Since we needed to integrate the whole T/R module system into a very small lattice spacing, we decided to use SiGe to integrate all the discrete components.”

During testing of the T/R module, the researchers realized that the receive mode of their system could operate at even lower frequencies – down to 5 GHz – giving it an operating range of 5 GHz to 50 GHz. Efforts are underway to expand the range of the transmit mode to accommodate a similarly wider frequency band.

The MAESTRO project is part of a GTRI initiative to use SiGe semiconductor technology for a variety of RF applications. The SiGe Multifunction IC for Radio Frequency (SMIRF) program is developing a wideband, multichannel, reconfigurable radio frequency transceiver integrated circuit using the SiGe technology. The goal is to enable element-level digital beamforming of an AESA for RF-converged multifunction systems to support concurrent operating modes such as radar, communications, electronic warfare, positioning, and signals intelligence (SIGINT).

MAESTRO has been supported by GTRI’s Independent Research and Development program.

Writer: John Toon (John.Toon@gtri.gatech.edu)

GTRI Communications

Georgia Tech Research Institute

Atlanta, Georgia USA

The Georgia Tech Research Institute (GTRI) is the nonprofit, applied research division of the Georgia Institute of Technology (Georgia Tech). Founded in 1934 as the Engineering Experiment Station, GTRI has grown to more than 2,800 employees, supporting eight laboratories in over 20 locations around the country and performing more than $700 million of problem-solving research annually for government and industry. GTRI's renowned researchers combine science, engineering, economics, policy, and technical expertise to solve complex problems for the U.S. federal government, state, and industry.

With his eighth and ninth papers published in this year’s IEEE International Symposium on High-Performance Computer Architecture (HPCA), Tushar Krishna has been inducted into the organization’s Hall of Fame. Only 10 members of the HPCA community were inducted to the Hall of Fame this year — a significant distinction reserved for researchers with eight or more papers appearing in the proceedings of the symposium.

The 28th HPCA Symposium took place virtually April 2-6, 2022, where Krishna, an associate professor in Georgia Tech’s School of Electrical and Computer Engineering (ECE), was honored. The Symposium is hosted by IEEE (Institute of Electrical and Electronics Engineers) and provides a high-quality forum for scientists and engineers to present their latest research findings in the rapidly changing field.

Krishna had two papers at HPCA 2022. The first was titled “MAGMA: An Optimization Framework for Mapping Multiple DNNs on Multiple Accelerator Cores”. ECE Ph.D. student Sheng-Chun Kao co-authored the paper. It presented a software scheduler for efficiently mapping multiple Deep Neural Networks (DNN) on emerging hardware platforms that include multiple AI accelerators. An AI Accelerator refers to specialized hardware optimized for running AI workloads.

The second paper, “Stay in your Lane: A NoC with Low-overhead Multi-packet Bypassing” was co-authored with collaborators from University of Toronto, Texas A&M University, and University of Wisconsin-Madison. It presented a technique for packets stuck at routers in networks on chip (NoC) due to congestion or deadlocks to progress to their destination via high-priority bypass paths.

His research team in Synergy Lab at Georgia Tech won the Best Paper Award at the 26th HPCA Symposium in 2020. The team’s award-winning paper, "SIGMA: A Sparse and Irregular GEMM Accelerator with Flexible Interconnects for DNN Training,” showcased SIGMA, a flexible and scalable AI Accelerator that offers high utilization of all its processing elements for Deep learning (DL) — the premier algorithmic technique for analyzing data across multiple domains, especially in visual understanding, speech perception, and automated reasoning.

Krishna has been an ECE faculty member since 2015 with an adjunct appointment in the School of Computer Science. He held the ON Semiconductor Junior Professorship in ECE from 2019-2021. He serves as an associate director for the Center for Research into Novel Computing Hierarchies (CRNCH). Krishna’s research spans computer architecture, interconnection networks, networks-on-chip (NoC), and deep learning accelerators – with a focus on optimizing data movement in modern computing systems. His research is funded via multiple awards from NSF, DARPA, IARPA, Department of Energy, Intel, Google, Facebook, Qualcomm and TSMC. His papers have been cited over 11,000 times. Three of his papers have been selected for IEEE Micro’s Top Picks from Computer Architecture, one more received an honorable mention, and four have won best paper awards. He received the “Class of 1940 Course Survey Teaching Effectiveness” Award from Georgia Tech in 2018 and the “Roger P. Webb Outstanding Junior Faculty Award” from the School of ECE in Georgia Tech in 2021.

Professor Sung Kyu Lim and his research team have won the 2022 Donald O. Pederson Best Paper Award for their paper “Compact-2D: A Physical Design Methodology to Build Two-Tier Gate-Level 3D ICs.” The prestigious award recognizes the best paper published in IEEE’s Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), the flagship journal of the IEEE Council on Electronic Design Automation (CEDA).

The paper presents a physical design tool named Compact-2D that automatically builds high-density and commercial-quality monolithic three-dimensional integrated circuits (3D ICs). Compact-2D offers first-of-its-kind algorithms and methodologies in partitioning, floorplanning, placement, routing, and timing closure, all targeting 3D ICs under stringent power, performance, and area optimization goals.

The pioneering design leverages the commercial tools readily available for the conventional 2D ICs and extends their capabilities while adding key missing tools to produce 3D IC designs. These extensions include new and better algorithms for physical design automation that simultaneously optimize x, y, and z-dimensions in the design space. With Compact-2D, the team produced 3D IC designs that outperform commercial-quality 2D IC designs for the first time and paved the way for widescale 3D IC proliferation.

Lim, Motorola Solutions Foundation Professor in the Georgia Tech School of Electrical and Computer Engineer (ECE), co-wrote the paper with Bon Woong Ku (former ECE Ph.D. student currently at Synopsys) and Kyungwook Chang (former ECE Ph.D. student currently teaching at Sungkyunkwan University).

The award, sponsored by the IEEE Council on Electronic Design Automation (CEDA), is based on the overall quality, the originality, the level of contribution, the subject matter, and the timeliness of the research. It will be presented to the Georgia Tech team at this year’s Design Automation Conference (DAC) taking place in July 10-14 in San Francisco.

Biomedical researchers develop and use organoids as a tool for studying human development and disease. These little lab-grown cultures mimic human organs and provide a sharp view of tissue development, drug interaction, and other biochemical functions, offering an innovative approach to personalized medicine.

“Getting detailed 3D images of these miniature models of organs, and getting a good look at how they change under different conditions or stimulation, can tell us a lot about how the body works,” said Shuichi Takayama, professor and Price Gilbert Jr. Chair in Regenerative Engineering and Medicine in the Wallace H. Coulter Department of Biomedical Engineering at Georgia Tech and Emory University. “It can tell us how diseases progress, or how mechanical forces and certain drugs may change or affect cellular behavior.”

The trick is in getting those detailed images. Fluorescence 3D microscopy has helped transform the study of organoids at the cellular and subcellular levels — though with a few drawbacks. Conventional methods are time consuming and don’t adequately capture the fast, dynamic, sometimes unpredictable cellular and tissue processes of these model systems.

Now, a team of Georgia Tech researchers has built a better system to quickly produce high-resolution 3D images in real time, providing a quantitative analysis of organoids. Led by Coulter BME Assistant Professor Shu Jia, their custom-built microscope can reconstruct a comprehensive 3D representation with a single camera image. They described their system in the journal Biosensors and Bioelectronics.

Jia’s new system builds on his lab’s growing body of work in next-generation imaging systems.  Conventional 3D imaging technologies rely on time-consuming, redundant scanning-based techniques, which can result in damaged cells and compromised images. Jia’s team has pioneered a faster light-field system that provides greater resolution and minimizes photo damage. Their new system does all of that and more.

“This latest system is novel because it is entirely custom-built for imaging at the tissue and animal scale,” said Jia, who earlier this year received a CAREER award from the National Science Foundation. “We built everything from scratch on an optical table.”

Adding a hybrid point-spread function to the new system allows researchers to capture scanning-free recordings of intact organoids in all of their dynamic glory in milliseconds instead of minutes or even hours using conventional methods. With a single camera image, Jia’s system can reconstruct a time-lapse observation of the 3D volume of the samples.

“We can look — cell by cell — throughout the entire organoid, in high spatial and time resolution, and see from multiple angles what happens as a result of an external perturbation, or a response to a specific drug, or any change in the overall environment,” Jia said.

He said the imaging systems coming out of his lab have the potential to transform conventional 3D microscopy.

“Because this is a custom-built system, it’s very flexible and adaptive,” he added. “It works with organoids, but similarly, it can work with animal models. I think we can extend this method to different areas of research. There are a number of potential collaborations we are exploring.”

This research was supported by the National Institutes of Health (grant Nos. R35GM124846 and AI116482) and the National Science Foundation (grant Nos. EFMA1830941 and 2145235). Any opinions, findings, and conclusions or recommendations expressed in this material are those of the authors and do not necessarily reflect the views of any funding agency.

Mason A. Chilmonczyk is the CEO and Co-founder of Andson Biotech, a startup that develops new sensors to discover the next groundbreaking cell and gene therapies. In the following Q&A, Chilmonczyk briefly discusses his work in the IEN cleanroom and gives advice to current and future users.

How long have you been using the IEN cleanroom?

I began using the IEN cleanroom eight years ago when I started my Ph.D. program at Georgia Tech and I am still using it today.

What tools have/do you use when you are in the cleanroom?

• Hitachi 4700 FE SEM
• SCS G3P8 Spinners
• Tystar Mini
• Vision RIE
• Unaxis RIE
• PlasmaTherm RIE
• PlasmaTherm ICP
• STS ICP
• Obducat Nanoimprinter
• ADT Dicing Saw

What is/has been your favorite project you have worked on in the IEN cleanroom?

My Ph.D. project, “The Dynamic Sampling Platform for Real-time Bioreactor Monitoring,” has been the most satisfying project I have worked on in the IEN cleanroom. I collaborated with my advisor, Mechanical Engineering Professor Andrei Fedorov, and we utilized the Nanoscribe to make micro-3d printed parts. This allowed me to take interesting SEM images using the Field Emissions Scanning Electron Microscopes. My Ph.D. project was probably the most satisfying to "complete," but I am still working on it to this day.

At the core of my work was a microfluidic mass exchanger that I built in the IEN cleanrooms at Georgia Tech. As a result of this project, Professor Fedorov and I co-founded the startup Andson Biotech. The company is growing, and we recently licensed the technology to enable better biopharmaceutical workflows.

What advice would you give to other researchers thinking about using a tool in the IEN cleanroom?

I would say to only use the cleanroom for your research if you have a burning desire to learn about MEMS/microfabrication or you have to do so for your project. There are very rarely "quick" projects inside cleanrooms. In general, I think if you have the opportunity to learn about anything new you should take that chance.

What is your favorite thing about the IEN cleanroom?

My favorite thing about the IEN cleanroom is the people I've met. Some of my best and longest-term friends have been made in these cleanrooms. I really miss working in the cleanroom as often as I used to, because I don't get to interact with all my best friends. Unfortunately, many of my original friends [from the cleanroom] have moved on to other things. While I miss seeing them, I love to see them succeed!

Learn more about Mason’s project, company, and technology - New Startup Makes Developing Gene Therapies Faster and Easier

In June, some of the world’s top technologists in the VLSI (Very Large-Scale Integration) industry will convene in Honolulu for the 2022 IEEE Symposium on VLSI Technology and Circuits, one of the premier symposiums for microelectronics and semiconductor research. Now in its 42^nd year, the VLSI Symposium offers attendees the opportunity to share and exchange ideas on the most relevant subjects in their fields and address current and future directions in the development of VLSI technology.

Given the continuing global semiconductor shortage, the theme of this year’s conference is “Technology and Circuits for the Critical Infrastructure of the Future.” Seven papers submitted by Georgia Tech faculty have been accepted and will be presented during the conference. Paper topics include Ferroelectric Memories, Resistive Memories, Embedded DRAM, and Power Converter based on GaN/Si. The contributing professors include Asif Khan, Arijit Raychowdhury, Shimeng Yu, and Suman Datta from Georgia Tech’s Institute of Electronics and Nanotechnology (IEN) and the School of Electrical and Computer Engineering (ECE).

In addition to presenting their papers, Datta and Yu are also organizing short courses on Monolithic and Heterogenous Integration and Advances in Application-Specific Computing Systems and Technologies. Muhannad Bakir will present on “2.5D and 3D Polylithic Integration Technologies” as part of the course on Monolithic and Heterogenous Integration.

“The VLSI Symposium is one of the most selective and prestigious venues to publish the latest advances in semiconductor technologies and circuits, and it has always had a strong industry presence,” said Raychowdhury, who also serves as the Steve W. Chaddick School Chair in ECE. “Our participation through multiple papers and invited talks is a clear testament of the depth and breadth of our research program. Congratulations to all of the students and faculty members who are making us proud through their impactful research.”

About the contributors:

Arijit Raychowdhury is the Steve W. Chaddick School Chair and Professor at ECE. His research interests include low power digital and mixed-signal circuit design, design of power converters, sensors and exploring interactions of circuits with device technologies. He holds more than 25 U.S. and international patents and has published over 80 articles in journals and refereed conferences. He holds a Ph.D. in electrical and computer engineering from Purdue University and a B.E. in electrical and telecommunication engineering from Jadavpur University in India.

Muhannad Bakir is the Dan Fielder Professor in ECE. His research interests include heterogeneous microsystem design and integration, including 2.5D and 3D ICs and packaging, advanced cooling and power delivery for emerging system architectures; electrical and photonic interconnect technologies; biosensor technologies and their integration with CMOS; and nanofabrication technologies. Bakir is an editor of IEEE Transactions on Electron Devices and an associate editor of IEEE Transactions on Components, Packaging and Manufacturing Technology.

Suman Datta will join the Georgia Tech faculty this fall as Joseph M. Pettit Chair in ECE and a Georgia Research Alliance (GRA) Eminent Scholar. He will also have a joint appointment with the School of Materials Science and Engineering (MSE). His research involves high-performance, heterogenous computing, brain-inspired computing, and collective state computing using advanced CMOS (complementary metal–oxide–semiconductor) and beyond-CMOS devices. He also focuses on the development of semiconductor technologies for other types of computing, including intermittent computing, cryogenic computing, and harsh environment computing.

Asif Khan is an assistant professor in ECE with a courtesy appointment in MSE. His research focuses on microelectronic devices, specifically on ferroelectric devices that address the challenges faced by the semiconductor industry due to the end of transistor miniaturization. His research group at Georgia Tech focuses on all aspects of ferroelectricity ranging from materials physics, growth, and electron microscopy to micro- and nano-fabrication of electronic devices, all the way to ferroelectric circuits and systems for artificial intelligence, machine learning, and data-centric applications.

Shimeng Yu is an associate professor in ECE. He has both a master’s and Ph.D. in electrical engineering from Stanford University and a B.S. in microelectronics from Peking University. His research interests lie in nanoelectronic devices and circuits for energy-efficient computing systems. His expertise is on the emerging non-volatile memories (e.g., RRAM, ferroelectrics) for different applications such as deep learning accelerator, neuromorphic computing, monolithic 3D integration, and hardware security.

The IEEE Symposium on VLSI Technology and Circuits is a five-day hybrid event known as the microelectronics industry’s premiere international conference integrating technology, circuits, and systems with a range and scope unlike any other conference. In addition to the technical presentations, the Symposium program will feature a demonstration session, evening panel discussions, joint focus sessions, short courses, workshops, and a special forum session that provides a focused discussion on a specific topic relevant to the Symposia theme. To learn more visit http://www.vlsisymposium.org.

The Institute for Electronics and Nanotechnology (IEN) at Georgia Tech has announced the winners for the 2022 Spring Core Facility Seed Grants. The primary purpose of this program is to give first- and second-year graduate students in diverse disciplines working on original and unfunded research in micro- and nano-scale projects the opportunity to access the most advanced academic cleanroom space in the Southeast. In addition to accessing the high-level fabrication, lithography, and characterization tools in the labs, the awardees will have the opportunity to gain proficiency in cleanroom and tool methodology and access the consultation services provided by research staff members in IEN. Seed Grant awardees are also provided travel support to present their research at a scientific conference.

In addition to student research skill development, this bi-annual grant program gives faculty with novel research topics the ability to develop preliminary data to pursue follow-up funding sources. The Core Facility Seed Grant program is supported by the Southeastern Nanotechnology Infrastructure Corridor (SENIC), a member of the National Science Foundation’s National Nanotechnology Coordinated Infrastructure (NNCI).

Since the start of the grant program in 2014, 78 projects from ten different schools in Georgia Tech’s Colleges of Engineering and Science, as well as the Georgia Tech Research Institute and three other universities, have been seeded.

The six winning projects in this round were awarded IEN cleanroom and lab access time to be used over the next year. In keeping with the interdisciplinary mission of IEN, the projects that will be enabled by the grants include research in semiconductor technology, metamaterials, quantum devices, polymer films, and materials analysis.

The Spring 2022 IEN Core Facility Seed Grant Award winners are:

Customized Nonlinear Metamaterials for Photon Upconversion
PI: Wenshan Cai | Student: Anjan Goswami
School of Electrical and Computer Engineering/School of Materials Science and Engineering

Fabricating Semiconductor Moiré Quantum Devices for Quantum Information Applications
PI: Zhigang Jiang | Student: Wei-Chen Wang
School of Physics

Enhancing Ferroelectric Switching Through Sputter Process Control in AlScN
PI: Lauren Garten | Student: John Wellington-Johnson
School of Materials Science and Engineering

Self-Repairing Polymeric Films as Artificial Solid-Electrolyte Interface Enabling Rechargeable Zinc Metal Batteries
PI: Seung Woo Lee | Student: Kun Ryu
George W. Woodruff School of Mechanical Engineering

New Applications of Raman Spectroscopy for Determining Sediment Provenance in the Southern Alps of New Zealand
PI: Karl Lang | Student: Dru-Ann Harris
School of Earth and Atmospheric Sciences

Next-generation Back-illuminated Silicon Photomultipliers with Multi-layer Antireflection Coatings on Textured Surface
PIs: Anna Erickson and Yuguo Tao | Student: Mackenzie Duce
George W. Woodruff School of Mechanical Engineering (Nuclear and Radiological Engineering Program)

The Southeastern Nanotechnology Infrastructure Corridor (SENIC), a member of the National Nanotechnology Coordinated Infrastructure (NNCI), is funded by NSF Grant ECCS-2025462.

Vascular diseases are public enemy number one: the leading killers worldwide, accounting for nearly a third of all human deaths on the planet.

Continuous monitoring of hemodynamics – blood flow through the vascular system – can improve treatments and patient outcomes. But deadly conditions like hypertension and atherosclerosis occur in long and twisting vascular system with arteries of varying diameter and curvature, and existing clinical devices are limited by their bulk, rigidity, and utility.

Georgia Institute of Technology researcher Woon-Hong Yeo and his collaborators are trying to improve the odds for patients with development of an implantable soft electronic monitoring system. Their new device, consisting of a smart stent and printed soft sensors, is capable of wireless real-time monitoring of hemodynamics without batteries or circuits.

“This electronic system is designed to wirelessly deliver hemodynamic data, including arterial pressure, pulse, and flow, to an external data acquisition system, and it is super small and thin, which is why we can use a catheter to deliver it, anywhere inside the body,” said Yeo, whose team released its study this week in the journal Science Advances.

Yeo added, smiling, “It’s like a stent with multiple tricks up its sleeve.”

For example, when this device is installed in a patient with atherosclerosis, in addition to expanding and preventing the artery from narrowing, like a traditional stent, restoring normal blood flow, it will also provide a constant flow of data.

“Now, once you have deployed a stent, you’re not sure if the problem was resolved and patients may come back with the same issue,” Yeo said. “It can be a defect of the stent, or an issue with stent deployment, or perhaps a problem with the patient’s blood flow.”

And the current standard way to monitor all of that is with an angiogram. That can be expensive and in rare instances, particularly with patients also struggling with diabetes, the dyes and radiation used in angiogram imaging can cause cancer. Yeo’s system seeks to circumvent the need for an angiogram or other imaging requirements.

His wireless smart stent platform, integrated with soft sensors, is operated by inductive coupling to offer wireless real-time monitoring that can detect a wide range of vascular conditions. Inductive coupling uses magnetic fields for wireless energy transfer. It’s similar to what’s happening when you use a wireless charger for your phone, smartwatch, or other devices – they are gaining energy from the magnetic field created by the charger.

“Basically, you can put this sensor system anywhere inside the body,” Yeo explained. “The other thing about this technology platform is, in addition to being an implantable sensor system, it can be used as a wearable system. Think about a smartwatch and how much of its bulk is taken up by circuits or batteries. If you remove all of that, you have a device that is thinner than a typical Band-Aid, an almost invisible health monitor that you can wear anywhere.”

That’s the long-range goal, anyway. So far, they’ve tested their wireless implantable system on animal models. However, there is still plenty of work to do. And Yeo also has the backing of the National Science Foundation to advance the technology. He recently received a 3-year, $400,000 grant from NSF focused on his printed nanomembrane sensors and bioelectronics for wireless and continuous monitoring of vascular health.

“We believe that the mechanical, material, and electrical design principles we develop, and the engineering and biosensing framework that results from this work, will advance the field of implantable electronics and biomedical systems,” Yeo said. “And the insights and knowledge we gain will be applicable for other physiological processes and challenges in biomedical science and engineering.”

CITATION: Robert Herbert, Hyo-Ryoung Lim, Bruno Rigo, Woon-Hong Yeo. "Fully implantable wireless batteryless vascular electronics with printed soft sensors for multiplex sensing of hemodynamics." Science Advances (May 2022)

DOI: 10.1126/sciadv.abm1175

COMPETING INTERESTS: Hyo-Ryoung and Yeo are the inventors for a pending U.S. patent application related to the work described here. The authors declare that they have no other competing interests.

FUNDING: American Heart Association (grant 19IPLOI34760577), National Institutes of Health (NIH R03EB028928).