Benjamin Klein received his B.S. and M.S. in Electrical Engineering from the University of Wisconsin-Madison in 1994 and 1995, respectively. He received his Ph.D. in Electrical Engineering from the University of Illinois – Urbana-Champaign in 2000. The subject of his doctoral dissertation was the theory and modeling of vertical-cavity surface-emitting lasers (VCSELs), which are a class of semiconductor laser used for telecommunications applications.

From 2000-2003, Klein worked as a postdoctoral researcher at the National Institute of Standards and Technology in Boulder, Colorado, working on the modeling and design of semiconductor quantum-dot based devices, including single photon emitters and single electron transistors. From 2003-2020 he was a faculty member at the Georgia Institute of Technology, first on the Savannah campus, and later in Atlanta. At the time of his departure from Georgia Tech, he was an Associate Professor and the Associate Chair for Graduate Affairs in the School of Electrical and Computer Engineering.

Jennifer Hasler received her B.S.E. and M.S. degrees in electrical engineering from Arizona State University in August 1991. She received her Ph.D. in computation and neural systems from California Institute of Technology in February 1997. Hasler is a professor at the Georgia Institute of Technology in the School of Electrical and Computer Engineering; Atlanta is the coldest climate in which Hasler has lived. Hasler founded the Integrated Computational Electronics (ICE) laboratory at Georgia Tech, a laboratory affiliated with the Laboratories for Neural Engineering. Hasler is a member of Tau Beta P, Eta Kappa Nu, and the IEEE.

Abhijit Chatterjee is a professor in the School of Electrical and Computer Engineering at Georgia Tech and a Fellow of the IEEE. He received his Ph.D in electrical and computer engineering from the University of Illinois at Urbana-Champaign in 1990. Chatterjee received the NSF Research Initiation Award in 1993 and the NSF CAREER Award in 1995. He has received six Best Paper Awards and three Best Paper Award nominations. His work on self-healing chips was featured as one of General Electric 's key technical achievements in 1992 and was cited by the Wall Street Journal. In 1995, he was named a Collaborating Partner in NASA's New Millennium project. In 1996, he received the Outstanding Faculty for Research Award from the Georgia Tech Packaging Research Center, and in 2000, he received the Outstanding Faculty for Technology Transfer Award, also given by the Packaging Research Center. In 2007, his group received the Margarida Jacome Award for work on VIZOR: Virtually Zero Margin Adaptive RF from the Berkeley Gigascale Research Center (GSRC). Chatterjee has authored over 400 papers in refereed journals and meetings and has 20 patents. He is a co-founder of Ardext Technologies Inc., a mixed-signal test solutions company and served as chairman and chief scientist from 2000-2002. He is currently directing research in mixed-signal/RF design and test funded by NSF, SRC, MARCO-DARPA, and industry, and he served as chair of the VLSI Technical Interest Group at Georgia Tech from 2010-2012. He co-leads the Samsung Center of Excellence in High-Speed Test, established at Georgia Tech in 2011.

Matthieu R. Bloch is a Professor in the School of Electrical and Computer Engineering. He received the Engineering degree from Supélec, Gif-sur-Yvette, France, the M.S. degree in Electrical Engineering from the Georgia Institute of Technology, Atlanta, in 2003, the Ph.D. degree in Engineering Science from the Université de Franche-Comté, Besançon, France, in 2006, and the Ph.D. degree in Electrical Engineering from the Georgia Institute of Technology in 2008. In 2008-2009, he was a postdoctoral research associate at the University of Notre Dame, South Bend, IN. Since July 2009, Bloch has been on the faculty of the School of Electrical and Computer Engineering, and from 2009 to 2013 Bloch was based at Georgia Tech Lorraine. His research interests are in the areas of information theory, error-control coding, wireless communications, and cryptography. Bloch has served on the organizing committee of several international conferences; he was the chair of the Online Committee of the IEEE Information Theory Society from 2011 to 2014, an Associate Editor for the IEEE Transactions on Information Theory from 2016 to 2019, and he has been on the Board of Governors of the IEEE Information Theory Society since 2016 and currently serves as the 2nd Vice-President. He has been an Associate Editor for the IEEE Transactions on Information Forensics and Security since 2019. He is the co-recipient of the IEEE Communications Society and IEEE Information Theory Society 2011 Joint Paper Award and the co-author of the textbook Physical-Layer Security: From Information Theory to Security Engineering published by Cambridge University Press.

Muhannad S. Bakir is the Dan Fielder Professor in the School of Electrical and Computer Engineering at Georgia Tech. He and his research group have received more than thirty paper and presentation awards including six from the IEEE Electronic Components and Technology Conference (ECTC), four from the IEEE International Interconnect Technology Conference (IITC), and one from the IEEE Custom Integrated Circuits Conference (CICC). Bakir’s group was awarded 2014 and 2017 Best Papers of the IEEE Transactions on Components Packaging and Manufacturing Technology (TCPMT). He is the recipient of the 2013 Intel Early Career Faculty Honor Award, 2012 DARPA Young Faculty Award, 2011 IEEE CPMT Society Outstanding Young Engineer Award, and was an Invited Participant in the 2012 National Academy of Engineering Frontiers of Engineering Symposium. Bakir is the co-recipient of the 2018 IEEE Electronics Packaging Society (EPS) Exceptional Technical Achievement Award "for contributions to 2.5D and 3D IC heterogeneous integration, with focus on interconnect technologies." He is also the co-recipient of the 2018 McKnight Foundation Technological Innovations in Neuroscience Awards. In 2020, Bakir was the recipient of the Georgia Tech Outstanding Doctoral Thesis Advisor Award.  
 
Bakir serves on the editorial board of IEEE Transactions on Components, Packaging and Manufacturing Technology (TCPMT) and IEEE Transactions on Electron Devices (TED). Dr. Bakir serves as a Distinguished Lecturer for IEEE EPS. 

Shimeng Yu is a professor of electrical and computer engineering at the Georgia Institute of Technology. He received the B.S. degree in microelectronics from Peking University in 2009, and the M.S. degree and Ph.D. degree in electrical engineering from Stanford University in 2011 and 2013, respectively. From 2013 to 2018, he was an assistant professor at Arizona State University.

Yu’s research interests are semiconductor devices and integrated circuits for energy-efficient computing systems. His expertise is on the emerging non-volatile memories (e.g., RRAM, ferroelectrics) for applications such as AI hardware, in-memory computing, 3D integration, etc.

Among Yu’s honors, he was a recipient of NSF Faculty Early CAREER Award in 2016, IEEE Electron Devices Society (EDS) Early Career Award in 2017, ACM Special Interests Group on Design Automation (SIGDA) Outstanding New Faculty Award in 2018, Semiconductor Research Corporation (SRC) Young Faculty Award in 2019, ACM/IEEE Design Automation Conference (DAC) Under-40 Innovators Award in 2020, IEEE Circuits and Systems Society (CASS) Distinguished Lecturer for 2021-2022, and IEEE EDS Distinguished Lecturer for 2022-2023, etc.

Yu is active in professional services. He served or is serving technical program committee for IEEE International Electron Devices Meeting (IEDM), IEEE Symposium on VLSI Technology and Circuits, ACM/IEEE Design Automation Conference (DAC), ACM/IEEE Design, Automation & Test in Europe (DATE), ACM/IEEE International Conference on Computer-Aided-Design (ICCAD), etc.  He is an editor of IEEE Electron Device Letters and a senior member of the IEEE.

Suresh Sitaraman is a Professor in the George W. Woodruff School of Mechanical Engineering, and leads the Flexible Hybrid Electronics Initiative at Georgia Tech and directs the Computer-Aided Simulation of Packaging Reliability (CASPaR) Lab at Georgia Tech. He is a Thrust Leader/Faculty Member, Reliability/Mechanical Design Research, 3D Systems Packaging Research Center; a Faculty Member, Georgia Tech Manufacturing Institute; a Faculty Member, Interconnect and Packaging Center, an SRC Center of Excellence, Institute for Electronics and Nanotechnology; a Faculty Member, Nanoscience and Nanotechnology, Nanotechnlogy Research Center, Institute for Electronics and Nanotechnology; a Faculty Member, Institute of Materials. Dr. Suresh Sitaraman's research is exploring new approaches to develop next-generation microsystems. In particular, his research focuses on the design, fabrication, characterization, modeling and reliability of micro-scale and nano-scale structures intended for microsystems used in applications such as aerospace, automotive, computing, telecommunicating, medical, etc. Sitaraman's research is developing physics-based computational models to design flexible as well as rigid microsystems and predict their warped geometry and reliability. His virtual manufacturing tools are able to simulate sequential fabrication and assembly process mechanics to be able to enhance the overall yield, even before prototypes are built. Sitaraman's work is developing free-standing, compliant interconnect technologies that can mechanically decouple the chip from the substrate without compromising the overall electrical functionality. This work is producing single-path and multi-path interconnect technologies as well as nanowire and carbon nanotube interconnects for electrical and thermal applications, and such interconnect technologies can be employed in flexible as well as 3D microelectronic systems. Sitaraman's research is also developing innovative material characterization techniques such as the stressed super layer technique as well as magnetic actuation test that can be used to study monotonic and fatigue crack propagation in nano- and micro-scale thin film interfaces. In addition, Sitaraman has developed fundamental modeling methodologies combined with leading-edge experimentation techniques to study delamination in the dielectric material and copper interface used in back-end-of-the-line (BEOL) stacks and through-silicon vias as well as epoxy/copper and epoxy/glass interfaces as in microelectronic packaging and photovoltaic module applications. Examining the long-term operational as well as accelerated thermal cycling reliability of solder interconnects, his work has direct implications in implantable medical devices, photovoltaic modules, computers and smart devices as well as rugged automobile and aerospace applications. Through the above-mentioned fundamental and applied research and development pursuits, Sitaraman's work aims to address some of the grand challenges associated with clean energy, health care, personal mobility, security, clean environment, food and water, and sustainable infrastructure

Oliver Pierron joined Georgia Tech in summer 2007. Prior, he was a senior engineer at the R&D center of Qualcomm MEMS Technologies, Inc. in San Jose, California. Pierron's research group investigates the mechanical properties of small-scale materials with emphasis on the degradation properties (fracture, fatigue, creep). The scientific contribution of this research is to develop a fundamental understanding of the degradation mechanisms at the nanoscale while the engineering motivation is to assess and predict the structural reliability of devices and systems fabricated with emerging technologies. An underlying challenge is to develop experimental techniques that permit to accurately measure these properties. Pierron's research is currently sponsored by the National Science Foundation.