Beginning in 2023, researchers applying for many sources of federal funding will be required to have a persistent identifier (an ORCID iD). Fortunately, there is an easy way to meet this requirement: creating an ORCID iD, which also adds value, including addressing more specific research activity disclosure requirements.

As a Georgia Tech researcher, you need to register with ORCID and connect it with Georgia Tech.

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Georgia Tech is a university that receives more than $50 million in federally funded research per year; therefore, we are required by the National Security Presidential Memorandum-33 (NSPM-33) to strengthen and standardize disclosure requirements for federally funded awards.The first step in protecting your research at Georgia Tech is to register and connect your ORCID iD with Georgia Tech. Learn more.

Absolics, Inc., a subsidiary of SKC Co., broke ground on a new semiconductor manufacturing facility in Covington, Georgia, on November 1. The $600 million facility will produce a revolutionary glass substrate that can “significantly increase the performance and energy efficiency of chipsets.” It is expected to create more than 400 skilled jobs in Georgia.

In a previous announcement about the facility, Georgia Tech President Ángel Cabrera said “We’re delighted that Georgia Tech’s investment in packaging research and advanced circuitry over the last 25-30 years has contributed to Georgia’s selection as the best place for the company to manufacture their state-of-the-art semiconductor technology. We look forward to further collaboration so we can work together to lead the region in developing the best engineering talent to work in this crucially important field.”

Georgia Tech 3D Systems Packaging Research Center (PRC) Director Madhavan Swaminathan and his team worked closely with SKC on this project. According to Swaminathan, glass as a substrate material has seven useful attributes or properties, namely smoothness which enables dense connectivity between chips; tailorable thermal expansion which improves reliability; stiffness which eases manufacturability; zero moisture absorption that improves stability; low thermal conductivity which isolates hotspots; dielectric insulation that improves performance; and large area panel processing which reduces cost.

“The PRC has been pioneering glass substrate technology for many years and we have been continuing to advance this technology working closely with SKC and several other supply chain companies along with state and federal support,” said Swaminathan, who also participated in the monumental groundbreaking ceremony. “With applications emerging in artificial intelligence, high-performance computing, and high-end communications, we expect glass substrates as being the next technology of the future. By creating the world’s first glass substrate factory, we see Absolics as being uniquely positioned to productize and commercialize this technology through their vast skill set, know-how, and customized manufacturable solutions. In the years ahead we look forward to continuing our close collaboration with Absolics in several areas that include research, education, and workforce development.”

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Muhannad Bakir has been named interim director of the Institute for Electronics and Nanotechnology’s Packaging Research Center (PRC). Bakir will assume this role on December 1, 2022.

"I am delighted that Professor Bakir has agreed to serve the campus community in this capacity,” said Michael Filler, IEN’s associate director for research programs. “His deep expertise in electronics packaging, proven leadership, and steady judgement will be an asset to PRC during this transition.”

The PRC is a graduated National Science Foundation Engineering Research Center focusing on advanced packaging and system integration leading to System on Package technologies. The Center conducts research and education in all aspects of electronics packaging that includes design, materials, process, assembly, thermal management, and integration driven by applications, which includes broad areas such as high-performance computing, artificial intelligence, automotive, broadband wireless, and space.

The PRC team consists of 29 faculty from five schools at Georgia Tech, 11 researchers and administrative staff, more than 50 graduate and undergraduate students, and several visiting engineers. This is enabled through collaboration with 48 industry and government organizations and 14 universities in North America, Europe, and Asia.

“I look forward to collaborating with the campus community in this new capacity to continue Georgia Tech’s leadership and forward-looking research initiatives in the areas of advanced packaging, heterogeneous integration, and 3D architectures with our partners in the industry and government,” said Bakir.

Bakir, who also serves as the Dan Fielder Professor in the School of Electrical and Computer Engineering and leads the Integrated 3D Systems Group, brings a wealth of experience to his new role as PRC interim director. He and his research group have received more than thirty paper and presentation awards including six from the IEEE Electronic Components and Technology Conference, four from the IEEE International Interconnect Technology Conference, and one from the IEEE Custom Integrated Circuits Conference (CICC). His group was also awarded the 2014 and 2017 Best Papers of the IEEE Transactions on Components Packaging and Manufacturing Technology.

Bakir is the recipient of the 2013 Intel Early Career Faculty Honor Award, 2012 DARPA Young Faculty Award, 2011 IEEE CPMT Society Outstanding Young Engineer Award, and was an Invited Participant in the 2012 National Academy of Engineering Frontiers of Engineering Symposium. He is the co-recipient of the 2018 IEEE Electronics Packaging Society Exceptional Technical Achievement Award “for contributions to 2.5D and 3D IC heterogeneous integration, with a focus on interconnect technologies.” He is also the co-recipient of the 2018 McKnight Foundation Technological Innovations in Neuroscience Awards. In 2020, Bakir was the recipient of the Georgia Tech Outstanding Doctoral Thesis Advisor Award.

Bakir serves as a senior area editor for the IEEE Transactions on Components, Packaging and Manufacturing Technology and was previously an Editor for IEEE Transactions on Electron Devices. He has also served as a Distinguished Lecturer for IEEE EPS.

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The Georgia Tech School of Electrical and Computer Engineering (ECE) will be a significant contributor to overall success of the nation’s goal to increase domestic semiconductor production and solidify its microelectronics workforce as collaborative efforts by industry and government come into focus.

The School’s established partnership with the Semiconductor Research Corporation (SRC), in particular, will be key to the country’s long-term semiconductor competitiveness. As specific plans and investment opportunities continue to be developed, Dr. Todd Younkin, SRC’s CEO and President, visited the Georgia Tech campus in Atlanta on October 20-21. SRC is a world-renowned, high technology-based consortium that serves as a crossroads of collaboration between technology companies, academia, government agencies, and SRC’s highly regarded engineers and scientists.

“At this specific moment in time, when the county and world are committed to innovation in semiconductor technologies, it’s critically important to address our significant challenges strategically and collaboratively,” said Arijit Raychowdhury, the ECE Steve W. Chaddick School Chair. “Without the leadership of SRC, many challenges would go unmet. Having Todd on campus to meet with students, researchers, and leadership is fundamental to our future plans together.”

Younkin joined the ECE Advisory Board at the start of this fiscal year (July 1, 2022). At SRC he leads a ~$90 million per year global research agenda supported by over 3,000 academic and industrial researchers, 27 international companies, and three U.S. government agencies (DARPA, NIST, and NSF).

Currently Georgia Tech is a partner in SRC’s Joint University Microelectronics Program (JUMP). JUMP supports long-term research focused on high performance, energy efficient microelectronics for end-to-end sensing and actuation, signal and information processing, communication, computing, and storage solutions that are cost-effective and secure. The program, launched under the direction of Younkin in 2018, has six multi-university, multi-disciplinary innovation centers with 137 faculty, 749 students, and 412 industrial engineering liaisons.

“Georgia Tech offers a unique combination of expertise and collaborative spirit that is an important part of any SRC program.” Younkin said during his visit. “The faculty prepares future engineers to hit the ground running when they enter the semiconductor engineering workforce, either in academia or industry. This is crucial in the face of the rapid changes occurring in the microelectronics landscape today.”

Younkin also praised Georgia Tech’s unique fabrication and packaging facilities. Few universities can support the entire microelectronics stack – from materials and devices to packaging and systems – like Georgia Tech does.

Raheem Beyah, the dean of the College of Engineering and Southern Company Chair, and Chaouki T. Abdallah, executive vice president for research at Georgia Tech, met with Younkin during the visit. Additionally, Younkin was able to discuss ECE’s Opportunity Research Scholars’ Program (ORS), an innovative undergraduate research program designed to enhance and expand the academic experience of undergraduate students majoring in ECE, with academic professionals, faculty members, and the talented ORS student researchers.

On the afternoon of Oct. 20, Younkin participated in an ECE Panel Discussion with fellow Advisory Board member Roland Sperlich of Texas Instruments and Fernando Mujica of Apple Inc. The panel, moderated by ECE Professor Muhannad Bakir, attracted around 80 students. During the panel, Younkin expressed the demand for engineers with good communication skills and emphasized the importance of diversity.

“In order for companies to develop market-ready solutions, it’s crucial they are talking the same language,” said Younkin. “Additionally, the field needs to further prioritize diversity and inclusiveness. Achieving an inclusive workforce that unlocks the talents inherent in all of us requires increasing the participation of women and under-represented minorities, as well as striking a balance between American citizens and talented people coming from other nations.”

Last year, SRC and the Defense Advanced Research Projects Agency (DARPA) announced JUMP 2.0, a new long-term university research collaboration that will advance information and communication technologies (ICT) critical to the country’s economic growth and national security. The program signifies a new chapter in SRC’s history of public-private partnership with DARPA, leading semiconductor and ICT companies, and the defense industrial base.

Like its predecessor, JUMP 2.0 will work with researchers at outstanding U.S. universities – including Georgia Tech – to create collaborative, multidisciplinary research centers. SRC and DARPA look to announce the JUMP 2.0 research centers in early 2023.

Suman Datta has received the Test of Time Award at the 2022 IEEE Symposium on VLSI Technology and Circuits. Datta is the Joseph M. Pettit Chair in Advanced Computing in the Georgia Tech School of Electrical and Computer Engineering (ECE) and a Georgia Research Alliance Eminent Scholar.

Datta, who holds a joint appointment with the School of Materials Science and Engineering, was honored this year along with his co-authors and former colleagues at Intel Corporation for his 2006 research, “Tri-Gate Transistor Architecture with High-k Gate Dielectrics, Metal Gates and Strain Engineering.” True to its name, the Test of Time Award recognizes papers that have established their significance in history by standing the test of time. The goal of the award is to honor impactful papers and promote their recognition in the Symposia’s community.

As transistor gets smaller, it gets harder to switch off the transistor effectively. In response, Datta and his former Intel colleagues formulated the Tri-Gate transistor technology that was first introduced commercially at the 22-nm technology node. The transistor architecture has scaled to the 5-nm node and remains the workhorse of all leading-edge logic technology.

The research was the first experimental demonstration of high-performance NMOS and PMOS Tri-gate transistors in which the channel strain, high-k gate dielectric, gate electrode work functions, epitaxial source-drain regions were co-optimized together with the fin dimensions (width and height) and the fin shape (trapezoidal versus rectangular). The paper illustrated how to combine the electrostatic benefit of the fully-depleted nonplanar transistor structure with high-permittivity gate dielectric, work-function engineered metal gate electrodes and high- strain-engineered high-mobility channel to demonstrate high-performance CMOS transistors.

In addition to receiving the Test of Time Award at the symposium, Datta organized a short course on Monolithic and Heterogenous Integration and Advances in Application-Specific Computing Systems and Technologies. His research group presented three papers at the symposium on A Thousand State Superlattice Ferroelectric Field Effect Transistor Analog Weight Cell (with Professor Shimeng Yu); BEOL Compatible Ferroelectric Routers for Run-time Reconfigurable Compute-in-Memory Accelerators (with Professor Shimeng Yu) and Multi-bit per-cell 1T SiGe Floating Body RAM for Cache Memory in Cryogenic Computing (with Professor Arijit Raychowdhury).

Now in it’s 42nd year, the IEEE Symposium on VLSI Technology and Circuits is known as the microelectronics industry’s premiere international conference integrating technology, circuits, and systems. The 2022 symposium convened this year in Honolulu, Hawaii.