On April 28, 2023, Azad Naeemi and Tushar Krishna were celebrated as the recipients of this year's Eta Kappa Nu (IEEE-HKN) Outstanding Teacher Awards.

HKN award recipients are determined by a majority vote of the graduating class of the Georgia Tech School of Electrical and Computer Engineering (ECE) undergraduate program. They recognize the central and crucial role of professors in training and motivating future electrical, computer and allied field student engineers.

Professor Naeemi received this year’s W. Marshall Leach/Eta Kappa Nu Outstanding Senior Teacher Award. Naeemi’s research crosses the boundaries of materials, devices, circuits, and systems investigating integrated circuits based on conventional and emerging nanoelectronic and spintronic devices and interconnects.

He holds the distinction of being the inaugural recipient of the IEEE Solid-State Circuits Society (SSCS) James D. Meindl Innovators Award. He has also received accolades such as the NSF CAREER Award, SRC Inventor Recognition Award, and multiple best paper awards at international conferences.

In recognition of his innovative use of educational technology, Professor Naeemi was honored by the Institute with the Class of 1934 Outstanding Innovative Use of Education Technology Award this year. His educational tools have greatly enhanced the learning experience of students studying quantum theory and semiconductor physics/devices worldwide.

Associate Professor Krishna was awarded the Richard M. Bass/Eta Kappa Nu Outstanding Junior Teacher Award. His research encompasses computer architecture, interconnection networks, networks-on-chip (NoC), and deep learning accelerators, with a particular emphasis on optimizing data movement in modern computing systems.

Krishna was inducted into the High-Performance Computer Architecture (HPCA) Hall of Fame in 2022, recognizing his significant contributions to the field. He has also been honored with the Class of 1940 Course Survey Teaching Effectiveness Award from Georgia Tech (2018) and the Roger P. Webb Outstanding Junior Faculty Award from the ECE (2021).

Naeemi and Krishna’s enduring impact on the School of ECE undergraduate program and the wider engineering community will forever be recognized with their names etched on the Eta Kappa Nu Outstanding Teacher Awards display in the Van Leer Building.

Georgia Tech researchers have created a wearable device to accurately measure obstructive sleep apnea — when the body repeatedly stops and restarts breathing for a period — as well as the quality of sleep people get when they are at rest.

Under conventional methods, people who are suspected of having some sleep issue or disorder must go to a medical facility, where they are monitored overnight and tethered to a series of wired probes that record brain, eye, and muscle activity.

The wearable sleep monitor patch developed by a team of researchers and clinicians, led by W. Hong Yeo, an associate professor and Woodruff Faculty Fellow in Georgia Tech’s George W. Woodruff School of Mechanical Engineering, is made of silicone and fits over the forehead, with a second, smaller silicone attachment that molds to the chin.

“A lot of people have this disorder, but they don’t know it because it’s very hard to diagnose right now,” Yeo said. “Current smartphone apps don’t capture the specific data doctors and clinicians study to determine if a patient has apnea, rendering them useless.”

Conventional existing sleep testing is occurring in sleep labs because of device limitations. This at-home wearable device could be the alternative to the more expensive medical procedures at sleep labs.

Yeo and his team, which included researchers from across Georgia Tech, Emory University School of Medicine, the University of Texas at Austin, the Icahn School of Medicine at Mount Sinai in New York, the Korea Institute of Materials Science, and the Korea Advanced Institute of Science and Technology, reported their findings in Science Advances in May.

Rising Prevalence

While there are two additional types of sleep apnea — central and complex — obstructive sleep apnea is the most common, Yeo said, explaining that in addition to snoring and arrested breathing episodes, it’s generally characterized by waking up suddenly, gasping for air or choking, and high blood pressure.

Lack of quality sleep can exacerbate other health issues in people with existing illnesses such as heart disease or diabetes, Yeo said. But even those who don’t have other health ailments can have serious complications from sleep apnea because the longer it goes undetected and untreated, the more it will affect their hearts and brains over time.

Seeing the toll sleep apnea was taking on the U.S. population, Yeo set out to apply his wearable device research to the industry with a wireless sleep monitoring patch system. 

The patches — which have an accuracy rate of 88.5% for sleep apnea detection — have the thickness of an adhesive bandage. Three embedded electronic sensors send signals wirelessly via Bluetooth to record brain, eye, and muscle activity. That data is relayed to an app on a smart device such as a phone or tablet for further study and evaluation.

The device can be used at home, negating the need to go to a sleep center or medical facility for overnight monitoring.

“A lot of people have this type of sleep disorder; they just don’t know it,” said Yeo, whose research is centered primarily in advancing healthcare through the development of biosensors and bioelectronics. “In the U.S., more than 18 million people have this type of sleep apnea. That’s basically one out of every 15 Americans, and those numbers are increasing over time.”

Underlying health issues are partly behind the increase, he said, but key drivers are the types of food and portion sizes of the modern American diet as well as stress.

There’s also an economic toll on the country. Poor sleep cost the U.S. economy $411 billion in lost productivity in 2015. That figure is projected to exceed $467 billion by 2030.

Predicting Sleep Apnea

Using artificial intelligence and machine learning, the technology behind the wearable device records the data to give a sleep score that determines if the patient has sleep apnea or if they are getting enough quality sleep.

In the study, when measured against a controlled group of eight sleep apnea patients whose issues were detected under conventional testing means, Yeo’s wireless patch detected sleep apnea with an accuracy rate of 88.5%. For comparison, an existing headband device on the market had an accuracy rate of about 71% and cannot measure muscle activities.

What’s more, the technology Yeo and his team developed, and the machine learning algorithms used, can predict the likelihood that a person who doesn’t show any symptoms of sleep apnea will develop it at some point.

“By looking at the data, we can say that, if you don’t change something right now — whether it’s diet or sleeping behavior or anything like that — you’re likely to develop sleep apnea because your numbers are bad,” he said.

Solving a Problem

The wireless patch solves a multipronged challenge to conventional testing methodology by addressing current patient issues with comfort, time, access, and cost.

The current process — called a PSG or polysomnography test — proves uncomfortable for some patients. That’s because they must sleep in a fixed position for fear of detaching any one of the 15 wired probes from their skin. Having any of those sensors detach from their bodies risks not capturing enough data for proper assessments.

It's also time consuming because the patient must go to a sleep center and spend the night being monitored by medical personnel. There can also be a lag to even get tested. Patients who don’t have severe symptoms or other high-risk, underlying factors such as heart disease or hypertension, often must wait after getting a referral from a doctor to be slotted for a bed at a sleep center, pending availability. Finally, the current detection method is costly to patients and insurance systems, tallying roughly $8,000 per person, per night.

“So that testing barrier is really high for regular people unless you are already sick, then they will screen you to avoid any severe conditions,” Yeo said. “But for people who don’t show symptoms, you won’t know whether you have the sleep disorder until it gets severe. We want to stop sleep apnea before it starts.”

CITATION: Woon-Hong Yeo, Shinjae Kwon, Hyeon Seok Kim, Kangkyu Kwon, Hodam Kim, Yun Soung Kim, Sung Hoon Lee, Young-Tae Kwon, Jae-Woong Jeong, Lynn Marie Trotti, Audrey Duarte. “At-home wireless sleep monitoring patches for the clinical assessment of sleep quality and sleep apnea.” Science Advances. May 24, 2023. doi/10.1126/sciadv.adg9671.

The Institute for Electronics and Nanotechnology (IEN) Office of Education and Outreach participated in the 2023 National Science Teaching Association (NSTA) conference, held in Atlanta on March 23-25, 2023. The NSTA is a community of science educators and professionals committed to best practices in teaching science and STEM and its impact on student learning.

During the conference, the IEN team, along with the National Nanotechnology Coordinating Office (NNCO) from Washington, D.C., shared the many opportunities available to educators to learn about and teach nanotechnology to their students. IEN also provided an optional tour of its micro- and nanofabrication cleanroom and its Materials Characterization Facility for conference attendees. During the tour attendees got a firsthand view of the work that takes place, the capabilities of the facility, and notable research accomplishments.

“Partnering with organizations like the NSTA gives us an opportunity to teach educators how they can incorporate nanotechnology in their classrooms,” said Mikkel Thomas, IEN’s associate director for education and outreach. “Since the conference was held in Atlanta, we were able to not only share the many programs we have with them but also showcase our facilities.”

As part of its mission to prepare the workforce of the future, IEN offers opportunities for educators to learn about and teach nanotechnology. This includes the Research Experiences for Teachers (RET) program for high school teachers and technical college faculty a paid opportunity to experience the excitement of nanotechnology research and share this experience in their classrooms. In addition, the Summer Nanoscience Institute for Middle School Teachers (NanoSIMST) is a five-day workshop in which teachers will learn about nanoscience, develop lesson plans, and receive hands-on activities that bring nanoscience into the classroom.

In addition, high school teachers that participated in IEN’S Summer 2022 RET program shared their experiences with attendees by presenting a talk at the conference. The RET program was funded by the National Science Foundation and is part of a larger program within the National Nanotechnology Coordinated Infrastructure (NNCI).

More than 150 academic, government, and industry experts gathered on Tuesday, May 2, in the Marcus Nanotechnology Building for Georgia Tech Chips Day. The event was designed to bring together experts in microelectronics to learn from each other, network, and discuss this rapidly changing field.

Hosted by the Institute for Electronics and Nanotechnology (IEN), Chips Day began with a recorded statement from U.S. Senator Jon Ossoff emphasizing the importance of microelectronics and semiconductor research and commending Georgia Tech for hosting the event.

The agenda included speakers with a wide variety of expertise, including Gregg Bartlett, chief technology officer of GlobalFoundries, Fayrouz Saad, director of public engagement for the CHIPS Program Office, and Victor Zhirnov, chief scientist of Semiconductor Research Corporation, among others. Multiple Georgia Tech faculty members also gave talks, including Chaouki Abdallah, executive vice president of research, and Arijit Raychowdhury, professor and chair of the School of Electrical and Computer Engineering.

During his keynote address, Bartlett discussed market trends in the semiconductor industry and the market focus and roadmap for GlobalFoundries, one of the world’s leading semiconductor manufacturers. He explained that GlobalFoundries’ core focuses are on innovation and differentiated platforms, including silicon photonics, FinFET, and feature-rich CMOS. Bartlett also noted that, due to the dynamic nature of the semiconductor market, success requires collaboration across research consortia and academic institutions, including events like Chips Day and the recent partnership on semiconductor research and workforce development signed with Georgia Tech.

"I am incredibly proud of the work that the IEN faculty, staff, students, and our industrial and governmental partners did to make Chips Day a success,” said Michael Filler, IEN’s associate director of research. “This event brought together some of the brightest minds in the semiconductor industry to share their ideas and collaborate on solutions to some of the most pressing challenges facing our field.”

Chips Day also included a ceremony honoring John Hooper (M.S. EE 1955, Ph.D. EE 1961), Georgia Tech Regents’ Professor emeritus and the founding director of the Microelectronics Research Center (MiRC), which is now IEN. It included an overview of Hooper’s career and accomplishments given by David Hertling, professor emeritus in the School of Electrical and Computer Engineering. Hooper’s children, Jeff and Christie, were also in attendance.

Hertling explained how Hooper worked with President Joseph Pettit in the 1980s to establish a strong microelectronics research presence at Georgia Tech. This included designing the MiRC, which was uniquely constructed as a resource center to enable faculty from all disciplines to engage in cutting-edge research. This model allowed Tech to attract top microelectronics talent and become a leader in the space. Thanks to Hooper’s efforts, among others, IEN is now home to one of the largest academic cleanrooms in the country and supports the research of more than 1,000 users per year from Georgia Tech, other academic institutions, industry, and government labs.

In addition to the talks, Chips Day included industry panels on economic and workforce development featuring thought leaders in these respective areas. Georgia Tech students participated in a poster session to give attendees a glimpse into their research and vendors showcased the latest products and solutions driving advancements in semiconductors and microelectronics.

“Georgia Tech is committed to advancing semiconductor research and development,” concluded Filler. “I am confident that the work that was done at Chips Day will help to ensure that the United States remains a leader in semiconductor innovation for years to come."

A team of researchers from Georgia Tech, Emory University, Morehouse School of Medicine, University of Georgia, the Center for Global Health Innovation, and the Technical College System of Georgia has been awarded $1 million over the course of two years from the U.S. National Science Foundation's Regional Innovation Engines, or NSF Engines, program. They are among the more than 40 unique teams to receive one of the first-ever NSF Engines Development Awards, which aim to help partners collaborate to create economic, societal, and technological opportunities for their regions.  

The team, “Advancing Health Equity and Diagnostic Technologies (GA) Development,” will use the award to support key institutional, corporate, government, education, and community partners to create an innovative ecosystem that will inspire, develop, and translate affordable and widely available point-of-care (POC) medical technologies to advance health equity throughout the southeast.

“The Southeastern U.S. has the lowest life expectancy in the nation, and there are significant health disparities along economic, educational, racial, and geographic divisions,” said Wilbur Lam, Georgia Tech professor, principal investigator, and innovation lead. “The team will work to build an ecosystem of partners to drive use-inspired research and technology translation in the area of POC diagnostics and wearables with strong community engagement to help address these areas and advance health equity.” 

The NSF Engines program is a transformational investment for the nation, ensuring the U.S. remains in the vanguard of competitiveness for decades to come. 

"These NSF Engines Development Awards lay the foundation for emerging hubs of innovation and potential future NSF Engines," said NSF Director Sethuraman Panchanathan. "These awardees are part of the fabric of NSF's vision to create opportunities everywhere and enable innovation anywhere. They will build robust regional partnerships rooted in scientific and technological innovation in every part of our nation. Through these planning awards, NSF is seeding the future for in-place innovation in communities and to grow their regional economies through research and partnerships. This will unleash ideas, talent, pathways and resources to create vibrant innovation ecosystems all across our nation." 

Led by Lam, the team aims to build an ecosystem to drive use-inspired research and technology translation for health equity and leverage relationships with underserved Georgia communities to inspire a technology roadmap and adopt new technologies.​ An annual event and comprehensive roadmap will drive sustainable technology translation, workforce development, and systemic education.  

The awardees span a broad range of states and regions, reaching geographic areas that have not fully benefited from the technology boom of the past decades. These NSF Engines Development Awards will help organizations create connections and develop their local innovation ecosystems within two years to prepare strong proposals for becoming future NSF Engines, which will each have the opportunity to receive up to $160 million.   

Launched by NSF's new Directorate for Technology, Innovation and Partnerships and authorized by the "CHIPS and Science Act of 2022," the NSF Engines program uniquely harnesses the nation's science and technology research and development enterprise and regional-level resources. NSF Engines aspire to catalyze robust partnerships to positively impact regional economies, accelerate technology development, address societal challenges, advance national competitiveness and create local, high-wage jobs. 

View a map of the NSF Engines Development Awards. More information can be found on the NSF Engines program website.  

NSF MEDIA REQUESTS: media@nsf.gov  

GEORGIA TECH MEDIA REQUESTS: georgia.parmelee@gatech.edu  

Semiconductors, or microchips, are vital to life in the modern world. They’re used in the microwave you heated your breakfast in this morning, the car you drove to work, the mobile phone you shouldn’t use while driving, the bank ATM you visited, and the screened device you’re reading this story on.

They’re in our TVs, refrigerators, and washing machines, helping us live comfortable lives. They also help us stay alive as part of the medical network, used in pacemakers, blood pressure monitors, and MRI machines, among other things. Also, our national economic and defense systems rely on them. Basically, semiconductors control and manage the flow of information in the machinery that keeps the world going.

And right now, at Georgia Tech, researchers are working to innovate chip technology to ensure that U.S. semiconductor development is globally competitive, reliable, sustainable, and resilient, today and in the future.

“If you look at semiconductors, or the whole area of computing, it spans across Georgia Tech — across many different schools and disciplines,” said Arijit Raychudhury, professor and Steve W. Chaddick Chair in the School of Electrical and Computer Engineering (ECE). “Starting with physics and chemistry, where we essentially learn how different types of materials will react, to materials science and engineering, to electrical engineering and computer engineering, to computer science.”

It's a diverse, multidisciplinary enterprise from bottom to top, Raychudhury noted. And there is still plenty of room at the bottom, as theoretical physicist Richard P. Feynman famously said more than 60 years ago, predicting that one day we’d be making things at the atomic level. We are. It’s a familiar realm to Victor Fung and his lab, where they are designing new materials for semiconductors from the ground up, atom by atom.

“We are interested in exploring how to translate the latest advances in AI and machine learning to aid in accelerating computational materials simulations and materials discovery,” said Fung, assistant professor in the School of Computational Science and Engineering. “We’ve been developing methods which can accurately predict a wide range of materials’ properties, to greatly facilitate high-throughput materials screening.”

Fung’s lab is using AI to discover previously unstudied materials with the electronic properties to build into chips. This approach to creating “designer” semiconductors would be significantly faster and cover more of the materials space than current methods.

Improving the Landscape

Smaller, more efficient, and more powerful are all part of the constantly evolving landscape in semiconductor research and development. It’s a very expensive landscape. While many chips are about the size of a fingernail, they are among the most complex human-made objects on Earth. Just building a semiconductor fabrication factory costs billions of dollars.

For a chemical engineer like Michael Filler, that sounds like opportunity.

“Chemical engineers think about how we produce products on a massive scale,” said Filler, associate professor in the School of Chemical and Biomolecular Engineering and associate director of the Institute for Electronics and Nanotechnology (IEN).

Filler, whose research involves the growing of semiconductor components, like transistors, from seed particles, is aiming to help democratize the process of chip development, bringing down the cost substantially while maintaining performance. In a not too distant future, that could mean an individual at home printing a chip on a machine similar to a 3D printer.

“Imagine a laser printer that can literally spit out custom electronics in a matter of minutes,” Filler said. “We’re big believers in the individual’s ability to be creative and know what they want to build for their applications. Ultimately, we’re interested in giving makers and prototypers opportunities to customize electronics.”

He’s in the right place for the far-reaching research he has in mind, adding, “We are so blessed with great facilities at Georgia Tech. It would be hard to imagine working somewhere else, because very few places have the diversity and quality of tooling we have here.”

IEN, which facilitates much of the semiconductor research at Georgia Tech, is based in the Marcus Nanotechnology Building, with its state-of-the-art micro/nano fabrication facilities such as the shared cleanroom space and a laser machine lab for micromachining.

But it is the range of expertise and creativity among faculty and students who are making IEN and Georgia Tech a thought leader in semiconductor research. This is evidenced by Tech’s recent grant of $65.7 million from the Semiconductor Research Corporation and the Defense Research Projects Agency to launch two new interdisciplinary research centers.

Events like Georgia Tech Chip Day (May 2) and Nanowire Week, an international gathering happening in Atlanta in October, also speak to Tech’s growing influence in this area.

Answering the Call

The Covid-19 pandemic clarified just how difficult it can be to make more chips. A shortage of semiconductors affected the supply of phones, computers, and other commonly used items during the global shutdown. Increased demand, depleted reserves, and too few manufacturing plants and workers significantly crippled the supply chain.

“The high degree of geographic concentration in certain parts of the semiconductor supply chain has recently created a heightened risk of supply interruptions,” said Chip White, Schneider National Chair in Transportation and Logistics and professor in the H. Milton Stewart School of Industrial and Systems Engineering (ISyE). “Such interruptions and resulting wild fluctuations in semiconductor demand can threaten the nation’s public health, defense, and economic security.”

With that in mind, translational supply chain research is going on in several places on campus, White said, including the Supply Chain and Logistics Institute and the NSF AI Research Institute for Advances in Optimization. White and his colleagues are developing software platforms for stress testing manufacturing supply chains. The goal is to identify vulnerabilities and risk mitigation procedures to design and operate next generation supply chains for critical industries such as the semiconductor industry, to improve global competitiveness and strike a balance between market forces and national security.

In an effort to address and feed the next generation demand for chips, the Biden administration recently launched a massive effort to outcompete China in semiconductor manufacturing, offering $39 billion in funding incentives for companies seeking to build plants in the U.S.

Another related area of importance in the ongoing development of semiconductors is growing the workforce of the future, and that includes a new wave of researchers. This is a role that Jennifer Hasler takes seriously.

“I have a strong interest and belief in mentoring,” said Hasler, ECE professor and founder of the Integrated Computational Electronics lab at Georgia Tech. She’s proven, theoretically at least, that the technology already exists to build a silicon-based version of the human cerebral cortex (which would cost billions of dollars to design and build), but one of her favorite roles is working with new, young faculty.

“It’s a personal thing for me, but it’s one of the coolest things I’m involved in,” she said. “When they come to Georgia Tech, they see how big this place is, bigger than a company. I like to say to them, ‘Let’s calm down, take a breath, you’re good, so let’s go make some cool stuff. Let’s get some momentum going.’”

For Raychowdhury, director of the new Center for the Co-Design of Cognitive Systems (part of the JUMP 2.0 program), developing the skilled workforce of the future means answering the call of the nation.

“This is one of the largest ECE departments in the country, with many, many talented students,” he said. “And given the need and shortage of skilled professionals in this particular area, I think it’s critical for us to create that kind of pipeline.” Last year, ECE undergraduate students started taking a new, two-semester course, sponsored by Apple, in which they actually build microprocessors from scratch.

“This is completely new,” Raychowdhury said. “It’s expensive to offer this course, but we plan to keep doing it and we’re in conversations with other companies that want to invest in workforce development. So, in addition to doing fantastic research, we want to be sensitive to the needs of the country and a new generation.”

Writer: Jerry Grillo